GitHub SSH 认证失败排查:端口、密钥与代理 问题我今天从 github 下拉一个仓库的时候,突然报错: 12345Connection closed by 20.205.243.166 port 22fatal: Could not read from remote repository.Please make sure you have the correct access rightsand the repository exists. 2025-12-19 Tooling #GitHub #SSH #troubleshooting
biriscv 处理器研究:NPC 周期扩增与 fetch 时序 biriscv_fetchbiriscv_fetch 是 biRISC-V CPU 的取指单元,位于 ICache 和 Decode 阶段之间,负责: 管理 PC (Program Counter) 向 ICache 发起取指请求 缓冲 ICache 返回的指令 处理分支跳转请求 支持 MMU(可配置) 下面的分析是没有支持 MMU 的。 branch 处理123456789101112131 2025-12-15 Computer Architecture #biriscv #NPC #microarchitecture
超标量处理器设计(一):基本概念与流水线对比 第一章 超标量处理器概述为什么需要超标量为了提高 IPC。 普通处理器流水线流水线概述流水线就是为了降低指令周期的时间,提高频率的手段。 流水线的划分一般根据场景,进行划分流水段,并且每一个阶段的延迟尽量相近。 指令间的相关性RAW:无法避免;WAR:可以避免,写到其它寄存器。WAW:同 WAR,也可以避免,写到其它寄存器。 控制相关:只能靠预测器预取,一旦预测错误,会带来严重的性能问题。 超标量 2025-12-04 Computer Architecture #microarchitecture #CPU #superscalar
RISC-V BOOM 分支预测器:组合逻辑与覆盖策略 预测器的组合逻辑级联代码实现所有预测器的连接(config-mixins.scala:603-609): 123456789101112// 初始输入(全0预测)val resp_in = (0.U).asTypeOf(new BranchPredictionBankResponse)// 组合逻辑链ubtb.io.resp_in(0) := resp_inbim.io.resp_in(0) 2025-12-02 Computer Architecture #branch prediction #microarchitecture #RISC-V BOOM
RISC-V BOOM 分支预测器:Loop Predictor 机制 loopThe Loop Predictor specializes in predicting loop exit branches.It learns the iteration count of loops and predicts the loop exit when the learned count is reached. Structure: Small table (16 set 2025-12-02 Computer Architecture #branch prediction #RISC-V BOOM #loop predictor
RISC-V BOOM 分支预测器:TAGE 核心思想 TAGE is the most advanced branch predictor in BOOM. It uses multiple prediction tables indexed by different history lengths to achieve high accuracy. Key Concepts: Multiple tables with geometrically 2025-12-02 Computer Architecture #branch prediction #RISC-V BOOM #TAGE
RISC-V BOOM 分支预测器:BTB 条目与并行读取 btbThe Branch Target Buffer (BTB) caches branch target addresses to provide fast prediction of where branches will go. Structure: Set-associative cache (default: 128 sets, 2 ways) Each entry stores: 2025-12-02 Computer Architecture #branch prediction #BTB #RISC-V BOOM
RISC-V BOOM 分支预测器:BIM 结构分析 bimThis module implements a Bimodal Branch Predictor using 2-bit saturating counters. The prediction is based on the MSB of the counter: Counter = 0 (00): Strongly Not Taken Counter = 1 (01 2025-12-02 Computer Architecture #branch prediction #RISC-V BOOM #BIM
RISC-V BOOM 分支预测器:uBTB 基本组成 ubtbThis is the set-associative variant of the Micro BTB, as opposed to the fully-associative FAMicroBTB. It uses indexed addressing like a cache. Structure: 256 sets by default (configurable) Each e 2025-12-02 Computer Architecture #branch prediction #RISC-V BOOM #uBTB
分支预测器研究(四):RISC-V BOOM 分支预测概览 Branch PredictionBOOM uses two levels of branch prediction: a fast Next-Line Predictor (NLP) a slower but more complex Backing Predictor (BPD) In this case, the NLP is a Branch Target Buffer and the 2025-11-27 Computer Architecture #branch prediction #microarchitecture #RISC-V BOOM